NBTI-Aware Nanoscaled Circuit Delay Assessment and Mitigation

As semiconductor manufacturing entered into nanoscale era, performance degradation due to Negative Bias Temperature Instability (NBTI) became one of the major threats to circuits reliability. In this paper, we present a model and analysis of NBTI impact on circuit delays. First, we model NBTI impact on gate intrinsic delay and output transition delay. The insights of our models reveal that NBTI causes additional 6.7% intrinsic and 3% output transition delays to a gate. Second, we analyze delays in the gates at the inputs and outputs of a circuit. Simulation results from several benchmark circuits show that under a given condition identical gates at the circuit outputs suffer from 3.33% additional delays as compared to gates at the circuit inputs. Third, we analyze different techniques at transistor and circuit levels to mitigate NBTI. From the analysis of mobility increment, gate oversizing, temperature reduction, and supply voltage increment techniques, we conclude that temperature reduction is the most effective to mitigate NBTI.